IBIS Macromodel Task Group

Meeting date: 01 Jul 2008

Members (asterisk for those attending):
  Ambrish Varma, Cadence Design Systems
  Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
  Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
  Brad Brim, Sigrity
  Brad Griffin, Cadence Design Systems
  David Banas, Xilinx
  Donald Telian, consultant
  Doug White, Cisco Systems
  Essaid Bensoudane, ST Microelectronics
  Fangyi Rao, ???
  Ganesh Narayanaswamy, ST Micro
  Gang Kang, Sigrity
  Hemant Shah, Cadence Design Systems
  Ian Dodd, Agilent
  Joe Abler, IBM
  John Angulo, Mentor Graphics
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
  Kumar
  Lance Wang, Cadence Design Systems
  Luis Boluna, Cisco Systems
  Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
  Mike Steinberger, SiSoft
* Mustansir Fanaswalla, Xilinx
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
* Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
  Ray Comeau, Cadence Design Systems
  Richard Mellitz, Intel
  Richard Ward, Texas Instruments
* Sam Chitwood, Sigrity
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence Design Systems
* Sid Singh, Extreme Networks
  Stephen Scearce, Cisco Systems
  Steve Pytel, Ansoft
  Syed Huq, Cisco Systems
  Syed Sadeghi, ST Micro
  Terry Jernberg, Cadence Design Systems
* Todd Westerhoff, SiSoft
  Vikas Gupta, Xilinx
  Vuk Borich, Agilent
* Walter Katz, SiSoft
  Zhen Mu, Cadence Design Systems


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Opens:

Mike L. will not be able to take minutes next week.


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Call for patent disclosure:

- No one declared a patent.


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Review of ARs:

- Walter send example of "Framis" model definition
  - Done

- Arpad send pointer to AMS examples
  - Done

- David Banas report Xilinx position on LTI assumption for SerDes
  - No update

- Arpad:  Write parameter passing syntax proposal (BIRD draft)
  for *-AMS models in IBIS that is consistent with the
  parameter passing syntax of the AMI models
  - TBD

- TBD:    Propose a parameter passing syntax for the SPICE
  - [External ...] also?
  - TBD

- Arpad:  Review the documentation (annotation) in the macro libraries.
  - Deferred until a demand arises or we have nothing else to do

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New Discussion:

Continued discussion of Electrical Model Description:
- Walter: There has been discussion about why other efforts were unsuccessful
  - The problem was that people just didn't "sign up"
  - For AMI, Cadence and SiSoft made sure other companies were in the loop
  - This did not happen with ICM or [External Model]
- Bob: We are not in concensus on EMD
  - In about 30 emails, people have been "talking past each other"
  - We need to limit the scope
- Walter: When we are done, people have to agree with what we are doing.
  - Arpad: The IBIS AMS extensions BIRD was voted, everyone agreed
- Arpad: Everyone will agree that we need a nodal format
  - Walter: We then have to do decide the blocks we need
  - Bob: It is best if there are no intrinsic elements, just blocks
  - Arpad: There was a proposal to have different views
- Todd: Views help when using a model over 12 months for different things
  - Sometimes we want "quick and dirty" simulations
  - Other times we want details
- Todd: There are plenty of simple hierarchical syntaxes out there
  - We should not pick a language with a lot of stuff that is not needed
  - Bob: Anything that looks like VHDL or VAMS should be rejected.

- Arpad: Should we poll to see what the group wants to accomplish, as Walter
  suggested?
  - Bob: Module interconnect syntax is on the right path
    - Solves high end and low end problems
  - Walter: We should limit ourselves to LTI blocks to solve interconnect
    - The netlisting language can be used for other things later

- Arpad: If we constrain ourselves to LTI now, we will be blocked in the future
  - Radek: Agree
  - Arpad: Parameters are handled as constants
    - Walter: In the future we can define a controlled resistance block
    - Bob: We could add a Berkeley SPICE universal block
  - Sam: The special LAPLACE format of EFGH controlled sources is needed
    - This makes a difference in the file size required
  - Walter: People tend to have S-param, pole-zero preferences
  - Sam: Give an S-param model to 2 simulators, get different time domain results

- Walter: Scott McMorrow had a cable with active elements in it
  - EMD kind of solves that problem
  - IBIS does not support a "repeater", like an inline IBIS buffer
  - Walter: There could be different views for different speeds.

Walter showed netlist formats:
- Parameter tree block oriented netlist format
- SPICE like format
  - Corners parameter has 3 values, typ,min,max
  - This would be translated to taret simulator formats
- Arpad: Is the view idea implemented?
  - Walter: Not yet
- Bob: The block format is unreadable
  - It looks like every block has type/min/max
  - There will be problems generating this
- Walter: Software will convert this both ways
  - EDA companies will have to say if they can convert

Arpad showed his VHDL-like format
- Port assignment is by name, but could be by order
- Walter and Todd expressed dislike of VHDL format
- Arpad: It helps to support views

- Walter: How to differentiate between mega and milli
  - Arpad: uppercase and lowercase M
- Todd: VHDL is heavily typed
- Arpad: Schematic tools would take care of this
- Todd: Not every company will want to go with VHDL
- Bob: Generic SPICE without typ/min/max should be fine
  - Walter: An example should be written
  - Arpad: We could start with Berkeley SPICE and beef it up
  - Walter: It has transistors and other junk
- Arpad: Does Berkeley SPICE have .model?
  - No. No W element either
- Bob: A better format would have more levels
  - Nodes should be passed by order

AR: Bob propose SPICE-like netlist format

Arpad: Would like to see view example
 
AR: Walter rework format proposal to include views

Next meeting: 08 Jun 2008 12:00pm PT

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